Monday, June 20 • 4:00pm - 4:25pm
Mlcached: Multi-level DRAM-NAND Key-value Cache

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We present Mlcached, multi-level DRAM-NAND keyvalue cache, that is designed to enable independent resource provisioning of DRAM and NAND flash memory by completely decoupling each caching layers. Mlcached utilizes DRAM for L1 cache and our new KVcache device for L2 cache. The index-integrated FTL is implemented in the KV-cache device to eliminate any inmemory indexes that prohibit the independent resource provisioning. We show that Mlcached is only 12.8% slower than a DRAM-only Web caching service in the average RTT with 80% L1 cache hit while saving twothirds of its TCO. Moreover, our model-based study shows that Mlcached can provide up to 6X lower cost or 4X lower latency at the same SLA or TCO, respectively.

Monday June 20, 2016 4:00pm - 4:25pm MDT
Denver Marriott City Center 1701 California Street, Denver, CO 80202

Attendees (2)